115 lines
3.9 KiB
C++
Vendored
115 lines
3.9 KiB
C++
Vendored
// infoware - C++ System information Library
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//
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// Written in 2016-2020 by nabijaczleweli <nabijaczleweli@gmail.com> and ThePhD <phdofthehouse@gmail.com>
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//
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// To the extent possible under law, the author(s) have dedicated all copyright and related
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// and neighboring rights to this software to the public domain worldwide. This software is
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// distributed without any warranty.
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//
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// You should have received a copy of the CC0 Public Domain Dedication along with this software.
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// If not, see <http://creativecommons.org/publicdomain/zero/1.0/>
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#include "infoware/cpu.hpp"
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#include "infoware/version.hpp"
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#include <iostream>
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#include <utility>
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static const char* cache_type_name(iware::cpu::cache_type_t cache_type) noexcept;
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static const char* architecture_name(iware::cpu::architecture_t architecture) noexcept;
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static const char* endianness_name(iware::cpu::endianness_t endianness) noexcept;
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int main() {
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std::cout << "Infoware version " << iware::version << '\n';
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{
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const auto quantities = iware::cpu::quantities();
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std::cout << "\n"
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" Quantities:\n"
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<< " Logical CPUs : " << quantities.logical << '\n'
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<< " Physical CPUs: " << quantities.physical << '\n'
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<< " CPU packages : " << quantities.packages << '\n';
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}
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{
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std::cout << "\n"
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" Caches:\n";
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for(auto i = 1u; i <= 3; ++i) {
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const auto cache = iware::cpu::cache(i);
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std::cout << " L" << i << ":\n"
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<< " Size : " << cache.size << "B\n"
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<< " Line size : " << cache.line_size << "B\n"
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<< " Associativity: " << static_cast<unsigned int>(cache.associativity) << '\n'
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<< " Type : " << cache_type_name(cache.type) << '\n';
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}
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}
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{
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std::cout << "\n"
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<< " Architecture: " << architecture_name(iware::cpu::architecture()) << '\n'
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<< " Frequency: " << iware::cpu::frequency() << " Hz\n"
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<< " Endianness: " << endianness_name(iware::cpu::endianness()) << '\n'
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<< " Model name: " << iware::cpu::model_name() << '\n'
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<< " Vendor ID: " << iware::cpu::vendor_id() << '\n';
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}
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{
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std::cout << std::boolalpha
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<< "\n"
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" Instruction set support:\n";
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for(auto&& set : {std::make_pair("3D-now!", iware::cpu::instruction_set_t::s3d_now), //
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std::make_pair("MMX ", iware::cpu::instruction_set_t::mmx), //
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std::make_pair("SSE ", iware::cpu::instruction_set_t::sse), //
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std::make_pair("SSE2 ", iware::cpu::instruction_set_t::sse2), //
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std::make_pair("SSE3 ", iware::cpu::instruction_set_t::sse3), //
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std::make_pair("AVX ", iware::cpu::instruction_set_t::avx)})
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std::cout << " " << set.first << ": " << iware::cpu::instruction_set_supported(set.second) << '\n';
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}
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std::cout << '\n';
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}
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static const char* cache_type_name(iware::cpu::cache_type_t cache_type) noexcept {
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switch(cache_type) {
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case iware::cpu::cache_type_t::unified:
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return "Unified";
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case iware::cpu::cache_type_t::instruction:
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return "Instruction";
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case iware::cpu::cache_type_t::data:
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return "Data";
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case iware::cpu::cache_type_t::trace:
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return "Trace";
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default:
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return "Unknown";
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}
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}
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static const char* architecture_name(iware::cpu::architecture_t architecture) noexcept {
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switch(architecture) {
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case iware::cpu::architecture_t::x64:
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return "x64";
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case iware::cpu::architecture_t::arm:
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return "ARM";
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case iware::cpu::architecture_t::itanium:
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return "Itanium";
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case iware::cpu::architecture_t::x86:
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return "x86";
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default:
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return "Unknown";
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}
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}
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static const char* endianness_name(iware::cpu::endianness_t endianness) noexcept {
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switch(endianness) {
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case iware::cpu::endianness_t::little:
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return "Little-Endian";
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case iware::cpu::endianness_t::big:
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return "Big-Endian";
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default:
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return "Unknown";
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}
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}
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